Probe structure coaxial elongated electrical conductor projecting from a support surface, apparatus for use thereof and methods of fabrication thereof

ABSTRACT

The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.

This application claims priority from Provisional Application U.S. Ser.No. 60/026,050 which was filed on Sep. 13, 1996.

CROSS REFERENCE TO RELATED APPLICATION

The teaching of U.S. application Ser. No. ______ filed on the same dayherewith entitled, “INTEGRATED COMPLIANT PROBE FOR WAFER LEVEL TEST ANDBURNIN” to Brian S. Beaman et al. and the teaching of U.S. applicationSer. No. ______ filed on the same day herewith entitled, “WAFER SCALEHIGH DENSITY PROBE ASSEMBLY, APPARATUS FOR USE THEREOF AND METHODS OFFABRICATION THEREOF” to Brian S. Beaman et al. is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention is directed to structures having a plurality ofdiscrete insulated elongated electrical conductors projecting from asupport surface which are useful as probes for testing of electricalinterconnections to electronic devices, such as integrated circuitdevices and other electronic components and particularly for testing ofintegrated circuit devices with rigid interconnection pads andmulti-chip module packages with high density interconnection pads andthe apparatus for use thereof and to methods of fabrication thereof.

BACKGROUND OF THE INVENTION

Integrated circuit (IC) devices and other electronic components arenormally tested to verify the electrical function of the device andcertain devices require high temperature burn-in testing to accelerateearly life failures of these devices. Wafer probing is typically done ona single chip site at temperatures ranging from 25 C-125 C while burn-inis typically done on diced and packaged chips at temperatures rangingfrom 80 C to 150 C. Wafer probing and IC chip burn-in at elevatedtemperatures of up to 200 C has several advantages and is becomingincreasingly important in the semiconductor industry. Simultaneoustesting of multiple chips on a single wafer has obvious advantages forreducing costs and increasing production throughput and is a logicalstep towards testing and burn-in of an entire wafer.

The various types of interconnection methods used to test these devicesinclude permanent, semi-permanent, and temporary attachment techniques.The permanent and semi-permanent techniques that are typically usedinclude soldering and wire bonding to provide a connection from the ICdevice to a substrate with fan out wiring or a metal lead frame package.The temporary attachment techniques include rigid and flexible probesthat are used to connect the IC device to a substrate with fan outwiring or directly to the test equipment.

The permanent attachment techniques used for testing integrated circuitdevices such as wire bonding to a leadframe of a plastic leaded chipcarrier are typically used for devices that have low number ofinterconnections and the plastic leaded chip carrier package isrelatively inexpensive. The device is tested through the wire bonds andleads of the plastic leaded chip carrier and plugged into a test socket.If the integrated circuit device is defective, the device and theplastic leaded chip carrier are discarded.

The semi-permanent attachment techniques used for testing integratedcircuit devices such as solder ball attachment to a ceramic or plasticpin grid array package are typically used for devices that have highnumber of interconnections and the pin grid array package is relativelyexpensive. The device is tested through the solder balls and theinternal fan out wiring and pins of the pin grid array package that isplugged into a test socket. If the integrated circuit device isdefective, the device can be removed from the pin grid array package byheating the solder balls to their melting point. The processing cost ofheating and removing the chip is offset by the cost saving of reusingthe pin grid array package.

The most cost effective techniques for testing and burn-in of integratedcircuit devices provide a direct interconnection between the pads on thedevice to a probe sockets that is hard wired to the test equipment.Contemporary probes for testing integrated circuits are expensive tofabricate and are easily damaged. The individual probes are typicallyattached to a ring shaped printed circuit board and support cantileveredmetal wires extending towards the center of the opening in the circuitboard. Each probe wire must be aligned to a contact location on theintegrated circuit device to be tested. The probe wires are generallyfragile and easily deformed or damaged. This type of probe fixture istypically used for testing integrated circuit devices that have contactsalong the perimeter of the device. This type of probe is also muchlarger than the IC device that is being tested and the use of this typeof probe for high temperature testing is limited by the probe structureand material set. This is described with reference to applicant'sco-pending U.S. application Ser. No. 08/754,869 filed on Nov. 22, 1996,the teaching of which is incorporated herein by reference.

Another technique used for testing IC devices comprises a thin flexcircuit with metal bumps and fan out wiring. The bumps are typicallyformed by photolithographic processes and provide a raised contact forthe probe assembly. The bumps are used to contact the flat or recessedaluminum bond pads on the IC device. An elastomer pad is typically usedbetween the back of the flex circuit and a pressure plate or rigidcircuit board to provide compliance for the probe interface. This typeof probe is limited to flexible film substrate materials that typicallyhave one or two wiring layers. Also, this type of probe does not providea wiping contact interface to ensure a low resistance connection.

The aluminum bond pads on a high density IC device are typicallyrectangular in shape and are recessed slightly below the surface of thepassivation layer. If the wiping action of the high density probe is notcontrolled, the probe contact may move in the wrong direction and shortto an adjacent aluminum bond pad or the probe contact may move off ofthe aluminum bond pad onto the surface of the passivation layer andcause an open connection.

The position of the probe tips must be controlled to ensure accuratealignment of the probes to the interconnection pads on the IC device.During high temperature burn-in testing, the thermal expansion mismatchbetween the probe structure and the IC device must be small to ensurethat the probe position does not vary significantly over the burn-intemperature range. Thermal expansion mismatch within the probe structurecan result in contact reliability problems.

The challenges of probing a single high density integrated circuitdevice are further multiplied for multi-chip and full wafer testingapplications. Probe fabrication techniques and material selection arecritical to the thermal expansion and contact alignment considerations.A small difference in the thermal expansion of the substrate, wafer, andprobe construction will cause misalignment of the probe tip to the wafercontact pad. Compliance of the probe structure is another criticalfactor. Slight variations in the wafer metalization, warpage of thewafer, and slight variations in the probe height contribute to the totalcompliance requirements for the probe structure.

As the processing power of IC devices increases, the number of I/O andspeed of the I/O signals increases to meet this need. The use of highspeed signals and high density connections on an integrated circuitdevice provides an increased challenge to accurately test the functionof the device. High inductance of the test probes and cross talk betweenprobes can severely limit the ability to test high speed and highdensity chip connections. The inductance of the test probe can bereduced by reducing the probe length or by providing a probe structurethat has a shield ground. The integral shielding also helps to reducethe cross talk between high density probes and reduces the need to placegrounded probes between signal probes.

U.S. Pat. No. 5,177,439, issued Jan. 5, 1993 to Liu et al., is directedto fixtures for testing bare IC chips. The fixture is manufactured froma silicon wafer or other substrate that is compatible with semiconductorprocessing. The substrate is chemically etched to produce a plurality ofprotrusions to match the I/O pattern on the bare IC chip. Theprotrusions are coated with a conductive material and connected todiscrete conductive fanout wiring paths to allow connection to anexternal test system. The probe geometry described in this patent doesnot provide a compliant interface for testing the aluminum bond pads onthe IC device and does not provide a wiping contact interface. Thesubstrate used for fabrication of this probe fixture is limited tosemiconductor wafers which are relatively expensive. The high densityprobe with controlled wipe can be fabricated on a variety of inexpensivesubstrate with the fanout wiring.

Applicant's co-pending U.S. application Ser. No. 08/754,869 filed onNov. 22, 1996, the teaching of which is incorporated herein by referencedescribes a high density test probe for integrated circuit devices. Theprobe structure described in this docket uses short metal wires that arebonded on one end to the fan out wiring on a rigid substrate. The wiresare encased in a compliant polymer material to allow the probes tocompress under pressure against the integrated circuit device. The wireprobes are sufficiently long and formed at an angle to prevent permanentdeformation during compression against the integrated circuit device.

OBJECTS

It is the object of the present invention to provide a probe for testingintegrated circuit devices and other electronic components that userigid bond pads for the interconnection means.

Another object of the present invention is to provide a probe structurethat is an integral part of the fan out wiring on the test substrate orother printed wiring means to minimize the electrical conductor lengthas well as the contact resistance of the probe interface.

A further object of the present invention is to provide a probe with acompliant interface to compensate for slight variations in the rigidbond pad heights on the IC device and variations in the height of theprobe contacts.

An additional object of the present invention is to provide a raisedprobe tip for contacting recessed surfaces on the IC device.

Yet an another object of the present invention is to provide a probestructure that has low inductance and low cross talk electricalproperties.

Yet a further object of the present invention is to provide a probestructure that has an improved true position tolerance.

Yet an additional object of the present invention is to provide a probestructure that can be used for high performance and high frequencysingle chip or multiple chip wafer testing.

SUMMARY OF THE INVENTION

A broad aspect of the present invention is a structure having asubstrate having a surface; a plurality of elongated electricalconductors extending away from the surface; the elongated electricalhave a dielectric coating; and each of the elongated electricalconductors having a first end affixed to the surface and a second endprojecting away from the surface.

A more specific aspect of the structure according to the presentinvention includes a coating of an electrically conductive materialdisposed on the dielectric coating.

Another more specific aspect of the structure according to the structureof the present invention includes a means for electricallyinterconnection the electrically conductive coating on at least a partof said plurality of elongated electrical conductors.

Another more particular aspect of the present invention is an apparatusfor using the structure to test an electronic device having a means forholding the structure, means for retractably moving the structuretowards and away from the electronic device so that the second endscontact electrical contact locations on the electronic device andsubstrate.

Another broad aspect of the present invention is a method of providing asubstrate having a surface; providing a plurality of elongatedelectrical conductors each having a first end and a second end; bondingeach of the first ends to the surface so that the second ends aredisposed away from the surface; forming a dielectric coating on theelongated electrical conductors.

Another more specific aspect of the method according to the presentinvention further includes forming a coating of an electricallyconductive material on the dielectric coating.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, and advantages of the presentinvention will become apparent upon further consideration of thefollowing detailed description of the invention when read in conjunctionwith the drawing figures, in which:

FIG. 1 shows a cross section of the preferred embodiment of the highperformance test probe attached to a substrate and pressed against thealuminum bond pads on an integrated circuit device.

FIGS. 2-6 show the processes used to fabricate the compliant test probeon a fan out wiring substrate.

FIG. 7 shows a cross section of another embodiment of the highperformance test probe.

FIG. 8 shows a cross section of another embodiment of the highperformance test probe.

FIG. 9 shows a cross section of another embodiment of the highperformance test probe.

FIG. 10 is a top view of a probe structure showing clusters for chipsites on a wafer of chips.

FIG. 11 schematically shares a variety of shapes of probe wires usefulto practice the present invention, such as “S” showed “C” shaped,continuously curved, piece wire curved, piece wire linear andcombinations thereof.

FIG. 12 schematically shows alternative embodiments of compliant framestructure (17) to support probe tip positioning structure (20) to bemaintaining in position and to move as the probe tip ends (16) move whenthey are moved into engagement with electronic pads (31).

FIG. 13 schematically shows an apparatus for moving the probes accordingto the present invention into an out of electrical engagement with aworkpiece, such as on integrated circuit (IC), being tested.

FIG. 14-17 shows an electrochemical method of fabricating the structuresaccording to the present invention.

FIG. 18-20 show different structures for forming a corner connection forthe outer conductors made by the method of FIGS. 14-17.

DETAILED DESCRIPTION

FIG. 1 shows a cross section of a test substrate (11) and a highperformance test probe (10) according to the present invention. The testsubstrate (11) provides a rigid base for attachment of the probes (10)and fan out wiring from the high density array of probe contacts to alarger grid of pins or other interconnection means to the equipment usedto electrically test the integrated circuit device. The fan outsubstrate can be made from various materials and constructions includingsingle and multi-layer ceramic with thick or thin film wiring, siliconwafer with thin film wiring, and epoxy glass laminate construction withhigh density copper wiring. The test probes (10) are attached to thefirst surface (12) of the substrate (11). The probes are used toelectrically contact the aluminum bond pads (31) on the device (30)which is being tested. The device (30) under test, is preferably an ICchip. The bond pads (31) which are typically aluminum are typicallyrecessed slightly below the surface of the passivation layer (32) of theintegrated circuit device (30). The geometry of the compliant test probe(10) is optimized to provide a wiping contact interface to penetrate theoxides on the surface of the aluminum bond pads (31) to provide a lowresistance connection.

The test probe (10) is attached directly to the fan out wiring (13) onthe first surface (12) of the substrate (11) to minimize the resistanceof the probe interface. The probe geometry is optimized to provide aflexible contact interface that controls the direction and length of thewiping action. The probe wire (15) is surrounded by a polymer material(72) that provides additional support and elasticity to the angled wire(15). The polymer material (72) preferably completely encases the probewire (15) and the first surface (12) of the substrate (11) between theprobes (10) with the exception of the probe tip (16). A thin layer ofelectrically conductive material (90) preferably covers the surface ofthe polymer material (72) surrounding the probe wire (15) to provide anindividual ground shield for each of the probe wires (15). Theelectrically conductive material layer (90) is connected to groundterminals (92) on the surface (12) of the substrate (11). Grounding theelectrically conductive material (90) substantially prevents cross talkbetween rapidly time varying electrical signals from inducing anundesired electrical signal on an adjacent probe conductor. Thethickness and composition of the polymer material (72) can be varied tochange the elastic and electrical properties of the high performanceprobe (10). As the compliant high density probe (10) is pressed againstthe IC device (30), the probe wire (15) rotates slightly and the probetip (16) slides along the surface of the bond pads (31) of the IC device(30). The length of the sliding or wiping action is restricted by theangle and length of the probe wire (15) and the amount of compression ofthe probe (10). Since each of the probes (10) is separated from theadjacent probes, thermal expansion of the polymer material (72) is not afactor for high temperature applications such as burn-in. The polymermaterial (72) can be, for example, polyimide, polyamid-imide andfluorinated polymers such as teflon.

FIG. 2 shows a process used to fabricate the high performance testprobe. A thermosonic wire bonder tool is used to attach ball bonds (14)to the fan out wiring (13) on the first surface (12) of the rigidsubstrate (11). The wire bonder tool uses a first ceramic capillary (40)to press the ball shaped end of the bond wire (41) against the firstsurface (12) of the substrate (11). Compression force and ultrasonicenergy are applied through the first capillary (40) tip and thermalenergy is applied from the wire bonder stage through the substrate (11)to bond the ball shaped end of the bond wire (41) to the fan out wiring(13) on the first surface (12) of the substrate (11). The bond wire (41)is positioned at an angle and a shear blade (42) is used to sever thebond wire (41) to create an angled segment of wire (15) protrudingvertically from the ball bond (14). The movement of the ceramiccapillary (40) is controlled during this process to provide a shortstraight section of the wire (43) that is perpendicular to the surfaceof the rigid substrate (11).

FIG. 3 shows (preferably an argon-ion) laser (50) used to melt the endsof the short straight sections of the wire (43) to create a ball shapedcontact (16). The smooth surface of the ball shaped contact (16) isideal for a wiping interface. The size of the ball shaped contact (16)on the end of the probe wire (15) is controlled by the laser powerdensity and the alignment of the focal point from the tip of thestraight wire section (43).

FIG. 4 shows the process used to coat the ends of the ball shaped probecontacts with a protective material (62). Protective material (62) canbe a polymer such as polyimide, polyamide. The substrate (11) ispositioned over the container (60) of liquid protective material (61)with the ball shaped contacts (16) submersed in the liquid (61). Afterthe probe tips (16) are covered with the protective material (62), thesubstrate (11) is repositioned and a temporary dam (70) is placed aroundthe array of probe wires (15) as shown in FIG. 5. The cavity formed bythe temporary dam (70) is filled with a liquid polymer material (71)that produces a thin coating of polymer (72) on the probe wires (15).The process is controlled to create a conformal, uniform thickness ofthe polymer material such as paralyne (72) on each of the probe wires(15) and the first surface (12) of the substrate (11) between the probewires (15). Alternatively, the probe structure (10) after depositing theprotective coating (62) on the ends of wires (15), can be emersed into asolution while an electric potential is applied to the wires (15) toelectrolytically deposit a polymer such as a polyimide onto the surfaceof the wires (15). Useful processes are described in U.S. Pat. No.5,152,880 and U.S. Pat. Nos. 5,021,129, 5,242,713 and 5,242,551, theteaching of which is incorporated herein by reference.

FIG. 6 shows the process step for adding the electrically conductivelayer (90) on the surface of the polymer material (72). The conductivelayer (90) can be added by electroless plating, electrophoretic plating,sputtering, or evaporation processes using palladium, chrome, copper, orother conductive materials. Conductive polymers can also be used as theground layer (90) on the surface of the insulating polymer material(72). After adding the conductive layer (90), the protective coating(62) on the probe tips (16) is removed to expose the ball shapedcontacts (16). Coating (62) can be a water soluble wax or other waxwhich can be later removed by commonly known techniques.

When an electroactive material such as polyimide is used for layer (72),electrically conductive layer (90) can be electrochemically deposited bythe methods described in U.S. Pat. No. 5,242,713, the teaching of whichis incorporated herein by reference. When a halogenated polymer materialsuch as perflorinated polymer, such as Teflon (Dupont RegisteredTrademark) is used as dielectric layer (70), an electrically conductivelayer can be electrochemically disposed thereon according to theteaching of U.S. Pat. No. 5,374,454, the teaching of which isincorporated herein by reference.

FIG. 7 shows a cross section of another embodiment of the highperformance test probe (110). This embodiment (110) uses the sameconstruction as the embodiment (10) of FIG. 1 without the conductivelayer (90) on the surface of the polymer material (72). While theelectrical performance of this embodiment is not as good as thepreferred embodiment, lower fabrication costs are the main advantage. Inthis embodiment the coating (72) can also be a material with highelasticity such as a stiff metal such as Invar, Cu/Invar/Cu, nickelwhich will enhance the flexibility of the elongated conductor (15).

FIG. 8 shows a cross section of another embodiment of the highperformance test probe (120). This embodiment uses a thin sheet (81)(preferably Invar) to control the accuracy of the probe tip (16)positions. Sheet (81) can be any material such as a metal, a polymer, aglass and a ceramic. Invar is chosen to provide a TCE that is closelymatched to the TCE of the silicon wafer IC (30) to be tested. Othermaterials with a TCE in the range of 2 to 8 ppm can also be used for thesurface layer (81). A plurality of holes (82) are formed in the thinsheet (81) and are aligned with the corresponding probe tips (16). Thethin Invar sheet (81) is supported by an elastomer frame (80)surrounding the array of probes. The thin Invar sheet (81) can also becoated or laminated with a thin layer of polymer material on both thetop and bottom sides to insulate the sheet (81) from the probe tip (16).

FIG. 9 shows a cross section of another embodiment of the highperformance test probe (130). This embodiment is similar to theembodiment of FIG. 7 in that it uses a thin Invar sheet (81) to controlthe accuracy of the probe tip (16) positions. This embodiment also usesa compliant conductive polymer (83), such as conductive siloxane or aconductive foam elastomer, to fill the cavity between the probe wires(15) that is formed by the elastomer frame (80) and the thin sheet (81).The compliant conductive polymer (83) is in contact with a groundterminal (92) on the first surface (12) of the substrate (11) andprovides a ground shield for each of the probe wires (15). Electricallyconductive polymers are described in U.S. Pat. No. 5,198,153, theteaching of which is incorporated herein by reference.

As shown in FIG. 13 a structure such as shown in FIG. 3 is immersed in atank (1302) containing an electrolytic solution (1304) such as describedin U.S. Pat. No. 5,152,880 to deposit a polyimide from polyimidesolution or a polyimide from a polyisomide as described in U.S. Pat.Nos. 5,021,129, 5,242,713 and 5,242,551, the teachings of which areincorporated herein by reference. As described in these patents theappropriate currents and biases are applied to the wires (15) byapplying the currents and voltages to contact pads such as contact pads(1317) which are electrically connected to each of the wires (15) toresult in a polymer coating 1402 of FIG. 14. The structure 1404 of FIG.14 with polymer coated wires (1406) can then be immersed in anelectrolytic solution such as described in U.S. Pat. No. 5,242,713 todeposit a metal coating such as a copper coating on the polymer coating1402. This can be achieved by replacing solution 1304 in FIG. 14 withthe solution of U.S. Pat. No. 5,242,713 and applying the appropriatebias and current to contact 1317 to result in the structure of FIG. 15with dielectric coating 1404 coated with electrical conductor 1502. Whenthe structure of FIG. 15 is removed from tank 1302, protective layer 62can be removed as described above to result in the structure of FIG. 16.

As described with reference to FIG. 9 the space between the elongatedconductors can be filled with a material (1704). The material can be anelectrically conductive polymer which provides a common electricalconnection between electrically conductive layer (1502) on elongatedconductors 15. The material 1704 can be electrically contacted bycontact pad (1702). Alternatively, material 1704 can be a dielectricmaterial filled with electrically conductive particles 1706 such asmetal particles. Alternatively, material (1704) can be a blend of adielectric polymer and an electrically conductive polymer.Alternatively, a sheet (1808) such as (81) of FIG. 9 can be disposedover the ends of the coaxial elongated conductor as shown in FIG. 18.Sheet (1808) can be an electrical conductor or a multilayer sheet havinga dielectric and electrical conductor layer. Sheet (1802) can be bondedto outer conductor (1502) with an electrically conductive adhesive orsolder bond at location (1804) to form a common electrical connectionbetween the outer conductors (1402) of each coaxial elongated conductor(1806). Electrical contact can be made to sheet (1802) such as at 1810to hold it at a fixed potential as described in the referencesincorporated herein by reference below. Substrate (11) can be designedso that electrically conductive pads (21) on surface (19) areelectrically connected to elongated conductors (15) to thereby provide abias for the electrochemical processes. Alternatively, as shown in FIG.15 of the electrochemical deposition of electrically conductive layer1502 is allowed to proceed long enough and if the electricallyconductive pads (1902) shown in FIG. 19 are close enough theelectrically conductive layers (1502) on adjacent elongated conductors(15) will bridge the gap between pads (1502) and merge as shown atlocation (1704) to form a common outer electrical conductor which can bebiased to a common potential as shown at location (1906). Alternatively,in FIG. 14 protection layer (62) can be eliminated. If the centerelongated conductor (15) is completely immersed in the solution of FIG.13, the conductor (15) will be completely coated with dielectric layer(1406) and electrically conductive layer (1502). The coated ends ofelongated conductor (15) are dipped into etchants to remove the layers1402 and 1502 at the ends to result in the structure of FIG. 17.Alternatively, a laser can be used to burn off or volatilize the layers1402 and 1502 at the ends of elongated conductors 15. Alternatively,these layers can be abraded away.

FIG. 17 schematically shows an apparatus for moving probe structure 10towards and away from electronic device 204 so that probe tips 210engage and disengage electrical contact locations 212 on electronicdevice 204. Probe 20 is mounted on to holder 200 having means 214 forapplying electric power to the probe tips 210. Electronic device 206 isheld on base 206. Holder 200 is physically connected to support 202which is converted to arm 208 which is converted to base 206. Support202 is adapted for use and down movement. Examples of an apparatus toprovide the means for support and up and down movement can be found inU.S. Pat. No. 5,439,161 and U.S. Pat. No. 5,132,613, the teachings ofwhich are incorporated herein by reference.

These electrically conductive polymers can be combined with elastomericmaterials to form elastomeric electrically conductive polymericmaterials.

Other embodiments of the high performance test probe are possible bychanging the geometry of the probe wire or the probe tip. The probe wirecan be angled, curved, or straight and the probe tip can be ball shaped,straight, or flattened.

The teaching of the following patent co-pending applications areincorporated herein by reference:

-   U.S. Pat. No. 5,371,654 entitled, “THREE DIMENSIONAL HIGH    PERFORMANCE INTERCONNECTION PACKAGE”;-   U.S. patent application Ser. No. 08/614,417 entitled, “HIGH DENSITY    CANTILEVERED PROBE FOR ELECTRONIC DEVICES”;-   U.S. patent application Ser. No. 08/641,667 entitled, “HIGH DENSITY    TEST PROBE WITH RIGID SURFACE STRUCTURE”;-   U.S. patent application Ser. No. 08/527,733 entitled,    “INTERCONNECTOR WITH CONTACT PADS HAVING ENHANCED DURABILITY”;-   U.S. patent application Ser. No. 08/752,469 entitled, “FOAMED    ELASTOMERS FOR WAFER PROBING APPLICATIONS AND INTERPOSER    CONNECTORS”;-   U.S. patent application Ser. No. 08/744,903 entitled, “INTEGRAL    RIGID CHIP TEST PROBE”;-   U.S. patent application Ser. No. 08/756,831 entitled, “HIGH    TEMPERATURE CHIP TEST PROBE”;-   U.S. patent application Ser. No. 08/756,830 entitled, “A HIGH    DENSITY INTEGRAL TEST PROBE AND FABRICATION METHOD”;-   U.S. patent application Ser. No. 08/754,869 entitled, “HIGH DENSITY    INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE    THEREOF”.

It is to be understood that the above described embodiments are simplyillustrative of the principles of the invention. Various othermodifications and changes may be devices by those of skill in the artwhich will embody the principles of the invention and fall within thespirit and scope thereof.

1.-49. (canceled)
 50. A method comprising providing a substrate having asurface; providing a plurality of elongated electrical conductors eachhaving a first end and a second end; bonding each of said first ends tosaid surface so that said second ends are disposed away from saidsurface; forming a dielectric coating on said elongated electricalconductors; further including forming a coating of an electricallyconductive material on said dielectric coating.
 51. A method comprising:providing a substrate having a surface, said surface having a pluralityof elongated electrical conductors each having a first end and a secondend, each a said first ends being affixed to said surface, each of saidsecond ends being disposed away from said surface; coating said secondends with a first material leaving an uncoated portion of said pluralityof elongated conductors; coating said elongated conductors with adielectric material.
 52. A method according to claim 51 furtherincluding disposing on said dielectric material a layer of electricallyconductive material.
 53. A method according to claim 52 wherein saidlayer of electrically conductive material is deposited by a methodselected from the group consisting of electroless plating, electrolyticplating, electrophoretic deposition and sputtering.
 54. A methodaccording to claim 53 further including removing said first material toexpose said elongated conductor at said second end.
 55. A methodcomprising: providing a substrate having a surface, said surface havinga plurality of elongated electrical conductors each having a first endand a second end, each a said first ends being affixed to said surface,each of said second ends being disposed away from said surface;disposing said substrate in a container containing a solution so thatsaid second ends are not disposed in said solution; said solution beinga solution from which a dielectric material can be electrochemicallydeposited onto an electrically biased surface; applying an electricalbias to said plurality of elongated electrical conductors to dispose onthat portion of each of said elongated electrical conductors emersed insaid solution a dielectric coating.
 56. A method according to claim 55further including disposing said substrate in a second solution fromwhich an electrically conductive material can be electrochemicallydeposited so that said dielectric coating is emersed in said secondsolution, applying a bias to said elongated electrical conductors tocoat said dielectric material with an electrically conductive material.57. A method according to claim 55 wherein said dielectric material isan electroactive material.
 58. A method comprising: providing asubstrate having a surface, said surface having a plurality of elongatedelectrical conductors each having a first end and a second end, each asaid first ends being affixed to said surface, each of said second endsbeing disposed away from said surface; coating said second ends with afirst material leaving an uncoated portion of said plurality ofelongated conductors; disposing said substrate in a container containinga solution; said solution being a solution from which a dielectricmaterial can be electrochemically deposited onto an electrically biasedsurface; applying an electrical bias to said plurality of elongatedelectrical conductors to dispose on that portion of each of saidelongated electrical conductors emersed in said solution a dielectriccoating.
 59. A method according to claim 58 further including disposingsaid substrate in a second solution from which an electricallyconductive material can be electrochemically deposited so that saiddielectric coating is emersed in said second solution, applying a biasto said elongated electrical conductors to coat said dielectric materialwith an electrically conductive material.
 60. A method according toclaim 59 further including removing said first material to expose saidelongated conductor at said second end. 61.-65. (canceled)
 66. A methodaccording to claim 49 wherein said dielectric coating is selected fromthe group consisting of polyimides, polyamide-imides, paralynes,polysiloxanes, epoxies, polyurathanes, perflorinated polymers, andpolypropylenes.
 67. A method according to claim 50 wherein said coatingof an electrically conductive material is selected from the groupconsisting of Cu, Au, Ag, Pt, Pd, Ni and combinations thereof.
 68. Amethod according to claim 50 further including means for electricallyinterconnecting said electrically conductive coating on at least a partof said plurality of elongated electrical conductors.
 69. A methodaccording to claim 68 wherein said means for electricallyinterconnecting at least a part of said plurality of elongatedelectrical conductors is an electrically conductive coating disposed onat least a part of said surface.
 70. A method according to claim 67wherein said electrically conductive coating on said plurality ofelongated conductors and electrically coating on said surface are asubstantially continuous coating.
 71. A method according to claim 70wherein said substantially continuous coating is selected from the groupconsisting of a sputter deposited coating, a plasma deposited coating,an electrolytically deposited coating, an electrolessly depositedcoating, and electrophoretically deposited coating.
 72. A methodaccording to claim 49 further including a means for maintaining saidplurality of said second ends in substantially fixed positions withrespect to a reference position.
 73. A method according to claim 49 or50 wherein said first end is affixed to said surface at an electricalcontact location.
 74. A method according to claim 72 wherein said meansfor maintaining is a sheet or material having a plurality of openingstherein through which said second ends project.
 75. A method accordingto claim 72 wherein said means for maintaining further including meansfor electrically interconnecting said electrically conductive coating onat least a part of said plurality of elongated electrical conductors.76. A method according to claim 49 wherein said second end has aprotuberance thereat.
 77. A method according to claim 74 wherein saidsheet is formed from a material selected from the group consisting of arigid material and a compliant material.
 78. A method according to claim74 wherein said sheet comprises a sheet of electrically conductivematerial having a plurality of through holes therein, said sheet ofmaterial contains a dielectric material to provide a means forpreventing said elongated electrical conductors from electricallycontacting said sheet of electrically conductive material.
 79. A methodaccording to claim 74 wherein said sheet is spaced apart from saidsurface by a flexible support.
 80. A method according to claim 79wherein said flexible support is selected from the group consisting of aspring and an elastomeric material.
 81. A method according to claim 50wherein said elongated electrical conductors have a shape selected fromthe group consisting of linear, piece wise linear, curved andcombinations thereof.
 82. A method according to claim 79 wherein saidsheet and said flexible support form a space containing said pluralityof elongated electrical conductors.
 83. A method according to claim 82wherein said space is filled with a flexible material.
 84. A methodaccording to claim 83 wherein said flexible material is an elastomericmaterial.
 85. A method according to claim 78 wherein said sheet has atop surface and a bottom surface and said through holes have a sidewall,said dielectric material coats said top surface and said bottom surfaceand said sidewall.
 86. A method according to claim 50 wherein saidplurality of elongated electrical conductors are distributed into aplurality of groups arranged in a regular pattern.
 87. A methodaccording to claim 50 wherein said plurality of elongated electricalconductors are distributed into a plurality of groups.
 88. A methodaccording to claim 86 wherein said plurality of groups are arranged inan array.
 89. A method according to claim 87 wherein said plurality ofgroups are arranged in an array.
 90. A method according to claim 50wherein said method that forms a probe for an electronic device.
 91. Amethod according to claim 90 wherein said electronic device is selectedfrom the group consisting of an integrated circuit chip and a packagingsubstrate.
 92. A method according to claim 88 wherein each of saidgroups corresponds to an integrated circuit chip on a substratecontaining a plurality of said integrated circuit chips.
 93. A methodaccording to claim 92 wherein said substrate containing said pluralityof integrated circuit chips is a wafer of said integrated circuit chips.94. An apparatus for using the method formed by the method of claim 50to test an electronic device comprising: for holding said apparatusformed by the method of claim 50, means for retractably moving saidapparatus formed by the method of claim 50 towards and away from saidelectronic device so that said second ends contact electrical contactlocations on said electronic device, and applying electrical signals tosaid elongated electrical conductors.
 95. An apparatus for using themethod formed by the method of claim 50 to test an electronic devicecomprising: holding said method of claim 50, retractably moving saidstructure formed by the method of claim 50 towards and away from saidelectronic device so that said second ends contact electrical contactlocations on said electronic device, and applying electrical signals tosaid elongated electrical conductors.
 96. A method according to claim 50wherein there is a protuberance at said second end.
 97. A methodaccording to 74 wherein said sheet comprises a sheet of electricallyconductive material having a plurality of first through holes therein,and a sheet of dielectric material having a plurality of second throughholes therein, said first through holes are aligned with said secondthrough holes, said first through holes have a smaller diameter thansaid second through holes to provide a means for preventing saidelongated electrical conductors from electrically contacting said sheetof electrically conductive material.
 98. A method according to claim 97wherein sheet or electrically conductive material has a first side and asecond side, said sheet of dielectric material is disposed on either ofsaid first side and said second side of said sheet of electricallyconductive material.
 99. A method according to claim 97 where there isdisposed on said first side and said second side of said sheet ofelectrically conductive material a layer of said dielectric material.100. A method according to claim 74 wherein said sheet comprises a sheetof rigid material having a plurality of through holes therein, saidsheet contains a dielectric material to provide a means for preventingsaid elongated electrical conductors from electrically contacting saidsheet of rigid material.
 101. A method according to claim 74 whereinsaid sheet comprises a sheet of dielectric material having a pluralityof through holes therein, said sheet contains a sheet of a rigidmaterial disposed in contact with said sheet of dielectric material,said sheet of rigid material has an opening therein exposing a pluralityor said through holes to provide a means for support of said dielectricmaterial.
 102. A method according to claim 101 wherein said sheet isspaced apart from said surface by a flexible support, said sheet ofrigid material is disposed on said flexible support.
 103. A methodaccording to claim 50 wherein said forming a dielectric coating on saidelongated electrical conductors is controlled to create said coating tobe substantially conformal having a substantially uniform thickness.104. A method according to claim 50 wherein said forming a coating of anelectrically conductive material on said dielectric coating iscontrolled to create said coating to be substantially conformal having asubstantially uniform thickness.
 105. A method according to claim 103wherein said forming a coating of an electrically conductive material onsaid dielectric coating is controlled to create said coating to besubstantially conformal having a substantially uniform thickness.
 106. Amethod according to claim 50 wherein said dielectric coating is ofsubstantially uniform thickness, conformally coating at least a portionof each of said plurality of elongated electrical conductors.
 107. Amethod according to claim 106 wherein said coating of an electricallyconductive material is of substantial uniform thickness conformallycoating at least a portion of said dielectric coating.